//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================
#ifndef __BVD1_H__
#define __BVD1_H__

//#pragma pack(4)

#include "timerbits.h"  // timer (OST and RTC) bit macros
#include "INTCBits.h"   // Interrupt Controller bit macros
#include "GPIO.H"		// GPIO Register Definitions and bit macros
#include "cken.h"		// Clock Enable CKEN bit macros

#define v_PerifBase (0x80000000)  /*KCONFIG_MEMORY_MAPPED_IO_BASE*/

#define CACHED_TO_UNCACHED_OFFSET		0x00000000

   ////////////////////////////////////////////////////
  /* DEVICE BASE ADDRESSES GROUPED BY FUNCTIONALITY */
 ////////////////////////////////////////////////////

//
// ZERO-BANK Note: Bulverde Does NOT provide us with an actual Zero-Bank like the SA1110;
//  instead, we will use this address for dcache flushing, which does not
//  require Phy mem to actually exist (see FlushDCache() )
//
#define ZBANK_BASE_PHYSICAL			0xE0000000
#define ZBANK_BASE_C_VIRTUAL		0x96500000
#define ZBANK_BASE_U_VIRTUAL		(ZBANK_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)

//
// Internal Memory - Storage (256 KB)
//
#define IM_STORAGE_BASE_PHYSICAL    0x5C000000
#define IM_STORAGE_BASE_C_VIRTUAL   0x90000000
#define IM_STORAGE_BASE_U_VIRTUAL   (IM_STORAGE_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)
//
// Internal Memory - Control (12 B)
//
#define IM_CONTROL_BASE_PHYSICAL    0x58000000
//#define IM_CONTROL_BASE_C_VIRTUAL   0x84100000
#define IM_CONTROL_BASE_U_VIRTUAL   (IM_CONTROL_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)

//
// Camera Peripheral
//
#define CMRA_BASE_PHYSICAL          0x50000000
//#define CMRA_BASE_C_VIRTUAL         0x9AC00000
#define CMRA_BASE_U_VIRTUAL         (CMRA_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)

//
// USB Host
//
#define USBH_BASE_PHYSICAL          0x4C000000
#define USBH_BASE_C_VIRTUAL         (((UInt32)v_PerifBase) + 0xC000000)
#define USBH_BASE_U_VIRTUAL         (USBH_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)

//
// MEMC
//
#define MEMC_BASE_PHYSICAL			0x48000000
#define MEMC_BASE_C_VIRTUAL			(((UInt32)v_PerifBase) + 0x8000000)
#define MEMC_BASE_U_VIRTUAL			(MEMC_BASE_C_VIRTUAL+CACHED_TO_UNCACHED_OFFSET)

//
// LCDC
//
#define LCD_BASE_PHYSICAL           0x44000000
#define LCD_BASE_C_VIRTUAL          (((UInt32)v_PerifBase) + 0x4000000)
#define LCD_BASE_U_VIRTUAL          (LCD_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)

//
// Perifs - DMAC, UART[3:1/SIR], I2S/C, AC97, USBC, FIR, RTC, OST, PWM, INTC, GPIO, PWRMAN/RESETC, SSP[3:1], MMC, CLKMAN, BB, KYPD, USIM, MEMSTICK
//
#define PERIF_BASE_PHYSICAL			0x40000000
#define PERIF_BASE_C_VIRTUAL		((UInt32)v_PerifBase)//0x80000000
#define PERIF_BASE_U_VIRTUAL		(PERIF_BASE_C_VIRTUAL+CACHED_TO_UNCACHED_OFFSET)


//
// PCMCIA Slots 0,1
//
#define PCMCIA_S0_IO_PHYSICAL		0x20000000
//#define PCMCIA_S0_IO_C_VIRTUAL		0x94500000	// cached & buffered virtual
#define PCMCIA_S0_IO_U_VIRTUAL		(PCMCIA_S0_IO_C_VIRTUAL+CACHED_TO_UNCACHED_OFFSET)

#define PCMCIA_S0_ATTR_PHYSICAL		0x28000000
//#define PCMCIA_S0_ATTR_C_VIRTUAL	0x92500000
#define PCMCIA_S0_ATTR_U_VIRTUAL	(PCMCIA_S0_ATTR_C_VIRTUAL+CACHED_TO_UNCACHED_OFFSET)

#define PCMCIA_S0_CMN_PHYSICAL		0x2C000000
//#define PCMCIA_S0_CMN_C_VIRTUAL		0x8E500000
#define PCMCIA_S0_CMN_U_VIRTUAL		(PCMCIA_S0_CMN_C_VIRTUAL+CACHED_TO_UNCACHED_OFFSET)

#define PCMCIA_S1_IO_PHYSICAL		0x30000000
//#define PCMCIA_S1_IO_C_VIRTUAL		0x8C500000
#define PCMCIA_S1_IO_U_VIRTUAL		(PCMCIA_S1_IO_C_VIRTUAL+CACHED_TO_UNCACHED_OFFSET)

#define PCMCIA_S1_ATTR_PHYSICAL		0x38000000
//#define PCMCIA_S1_ATTR_C_VIRTUAL	0x8A500000
#define PCMCIA_S1_ATTR_U_VIRTUAL	(PCMCIA_S1_ATTR_C_VIRTUAL+CACHED_TO_UNCACHED_OFFSET)

#define PCMCIA_S1_CMN_PHYSICAL		0x3C000000
//#define PCMCIA_S1_CMN_C_VIRTUAL		0x86500000
#define PCMCIA_S1_CMN_U_VIRTUAL		(PCMCIA_S1_CMN_C_VIRTUAL+CACHED_TO_UNCACHED_OFFSET)



/////////////////////////////////////////////////////////////////////////////////////////
/* PERIPHERAL OFFSETS */
/////////////////////////////////////////////////////////////////////////////////////////

#define DMAC_OFFSET                     0x0             // DMA CONTROLLER
#define FFUART_OFFSET                   0x00100000      // Full-Feature UART
#define BTUART_OFFSET                   0x00200000      // BlueTooth UART
#define I2C_OFFSET                      0x00300000      // I2C
#define I2S_OFFSET                      0x00400000      // I2S
#define AC97_OFFSET                     0x00500000      // AC97
#define UDC_OFFSET                      0x00600000      // UDC (usb client)
#define STUART_OFFSET                   0x00700000      // Standard UART
#define FIR_OFFSET                      0x00800000      // FIR
#define RTC_OFFSET                      0x00900000      // real time clock
#define OST_OFFSET                      0x00A00000      // OS Timer
#define PWM0_2_OFFSET                   0x00B00000      // PWM 0 (pulse-width mod)
#define PWM1_3_OFFSET                   0x00C00000      // PWM 1 (pulse-width mod)
#define INTC_OFFSET                     0x00D00000      // Interrupt controller
#define GPIO_OFFSET                     0x00E00000      // GPIO
#define PWR_OFFSET                      0x00F00000      // Power Manager and Reset Control
#define SSP1_OFFSET                     0x01000000      // SSP 1
#define MMC_OFFSET                      0x01100000      // MMC
#define CLK_OFFSET                      0x01300000      // Clock Manager
#define BB_OFFSET                       0x01400000      // Baseband Interface
#define KYPD_OFFSET                     0x01500000      // Keypad Interface
#define USIM_OFFSET                     0x01600000      // USIM
#define SSP2_OFFSET                     0x01700000      // SSP 2
#define MEMSTK_OFFSET                   0x01800000      // Memory Stick
#define SSP3_OFFSET                     0x01900000      // SSP 3

/////////////////////////////////////////////////////////////////////////////////////////
/* DEVICE-SPECIFIC Address DEFINITIONS */
/////////////////////////////////////////////////////////////////////////////////////////

#define DMAC_BASE_PHYSICAL              (PERIF_BASE_PHYSICAL + DMAC_OFFSET)
#define DMAC_BASE_C_VIRTUAL             (PERIF_BASE_C_VIRTUAL + DMAC_OFFSET)
#define DMAC_BASE_U_VIRTUAL             (PERIF_BASE_U_VIRTUAL + DMAC_OFFSET)

#define FFUART_BASE_PHYSICAL			(PERIF_BASE_PHYSICAL + FFUART_OFFSET)
#define FFUART_BASE_C_VIRTUAL           (PERIF_BASE_C_VIRTUAL + FFUART_OFFSET)
#define FFUART_BASE_U_VIRTUAL           (PERIF_BASE_U_VIRTUAL + FFUART_OFFSET)

#define BTUART_BASE_PHYSICAL			(PERIF_BASE_PHYSICAL + BTUART_OFFSET)
#define BTUART_BASE_C_VIRTUAL			(PERIF_BASE_C_VIRTUAL + BTUART_OFFSET)
#define BTUART_BASE_U_VIRTUAL			(PERIF_BASE_U_VIRTUAL + BTUART_OFFSET)

#define STUART_BASE_PHYSICAL			(PERIF_BASE_PHYSICAL + STUART_OFFSET)
#define STUART_BASE_C_VIRTUAL           (PERIF_BASE_C_VIRTUAL + STUART_OFFSET)
#define STUART_BASE_U_VIRTUAL           (PERIF_BASE_U_VIRTUAL + STUART_OFFSET)

#define I2C_BASE_PHYSICAL               (PERIF_BASE_PHYSICAL + I2C_OFFSET)
#define I2C_BASE_C_VIRTUAL              (PERIF_BASE_C_VIRTUAL + I2C_OFFSET)
#define I2C_BASE_U_VIRTUAL              (PERIF_BASE_U_VIRTUAL + I2C_OFFSET)

#define I2S_BASE_PHYSICAL               (PERIF_BASE_PHYSICAL + I2S_OFFSET)
#define I2S_BASE_C_VIRTUAL              (PERIF_BASE_C_VIRTUAL + I2S_OFFSET)
#define I2S_BASE_U_VIRTUAL              (PERIF_BASE_U_VIRTUAL + I2S_OFFSET)

#define AC97_BASE_PHYSICAL              (PERIF_BASE_PHYSICAL + AC97_OFFSET)
#define AC97_BASE_C_VIRTUAL             (PERIF_BASE_C_VIRTUAL + AC97_OFFSET)
#define AC97_BASE_U_VIRTUAL             (PERIF_BASE_U_VIRTUAL + AC97_OFFSET)

#define UDC_BASE_PHYSICAL               (PERIF_BASE_PHYSICAL + UDC_OFFSET)
#define UDC_BASE_C_VIRTUAL              (PERIF_BASE_C_VIRTUAL + UDC_OFFSET)
#define UDC_BASE_U_VIRTUAL              (PERIF_BASE_U_VIRTUAL + UDC_OFFSET)

#define FIR_BASE_PHYSICAL               (PERIF_BASE_PHYSICAL + FIR_OFFSET)
#define FIR_BASE_C_VIRTUAL              (PERIF_BASE_C_VIRTUAL + FIR_OFFSET)
#define FIR_BASE_U_VIRTUAL              (PERIF_BASE_U_VIRTUAL + FIR_OFFSET)

#define RTC_BASE_PHYSICAL               (PERIF_BASE_PHYSICAL + RTC_OFFSET)
#define RTC_BASE_C_VIRTUAL              (PERIF_BASE_C_VIRTUAL + RTC_OFFSET)
#define RTC_BASE_U_VIRTUAL              (PERIF_BASE_U_VIRTUAL + RTC_OFFSET)

#define OST_BASE_PHYSICAL               (PERIF_BASE_PHYSICAL + OST_OFFSET)
#define OST_BASE_C_VIRTUAL              (PERIF_BASE_C_VIRTUAL + OST_OFFSET)
#define OST_BASE_U_VIRTUAL              (PERIF_BASE_U_VIRTUAL + OST_OFFSET)

#define PWM0_2_BASE_PHYSICAL            (PERIF_BASE_PHYSICAL + PWM0_2_OFFSET)
#define PWM0_2_BASE_C_VIRTUAL           (PERIF_BASE_C_VIRTUAL + PWM0_2_OFFSET)
#define PWM0_2_BASE_U_VIRTUAL           (PERIF_BASE_U_VIRTUAL + PWM0_2_OFFSET)

#define PWM1_3_BASE_PHYSICAL            (PERIF_BASE_PHYSICAL + PWM1_3_OFFSET)
#define PWM1_3_BASE_C_VIRTUAL           (PERIF_BASE_C_VIRTUAL + PWM1_3_OFFSET)
#define PWM1_3_BASE_U_VIRTUAL           (PERIF_BASE_U_VIRTUAL + PWM1_3_OFFSET)

#define INTC_BASE_PHYSICAL              (PERIF_BASE_PHYSICAL + INTC_OFFSET)
#define INTC_BASE_C_VIRTUAL             (PERIF_BASE_C_VIRTUAL + INTC_OFFSET)
#define INTC_BASE_U_VIRTUAL             (PERIF_BASE_U_VIRTUAL + INTC_OFFSET)

#define GPIO_BASE_PHYSICAL              (PERIF_BASE_PHYSICAL + GPIO_OFFSET)
#define GPIO_BASE_C_VIRTUAL             (PERIF_BASE_C_VIRTUAL + GPIO_OFFSET)
#define GPIO_BASE_U_VIRTUAL             (PERIF_BASE_U_VIRTUAL + GPIO_OFFSET)

#define PWR_BASE_PHYSICAL               (PERIF_BASE_PHYSICAL + PWR_OFFSET)
#define PWR_BASE_C_VIRTUAL              (PERIF_BASE_C_VIRTUAL + PWR_OFFSET)
#define PWR_BASE_U_VIRTUAL              (PERIF_BASE_U_VIRTUAL + PWR_OFFSET)

#define SSP1_BASE_PHYSICAL              (PERIF_BASE_PHYSICAL + SSP1_OFFSET)
#define SSP1_BASE_C_VIRTUAL             (PERIF_BASE_C_VIRTUAL + SSP1_OFFSET)
#define SSP1_BASE_U_VIRTUAL             (PERIF_BASE_U_VIRTUAL + SSP1_OFFSET)

#define MMC_BASE_PHYSICAL               (PERIF_BASE_PHYSICAL + MMC_OFFSET)
#define MMC_BASE_C_VIRTUAL              (PERIF_BASE_C_VIRTUAL + MMC_OFFSET)
#define MMC_BASE_U_VIRTUAL              (PERIF_BASE_U_VIRTUAL + MMC_OFFSET)

#define CLK_BASE_PHYSICAL               (PERIF_BASE_PHYSICAL + CLK_OFFSET)
#define CLK_BASE_C_VIRTUAL              (PERIF_BASE_C_VIRTUAL + CLK_OFFSET)
#define CLK_BASE_U_VIRTUAL              (PERIF_BASE_U_VIRTUAL + CLK_OFFSET)

#define BB_BASE_PHYSICAL                (PERIF_BASE_PHYSICAL + BB_OFFSET)
#define BB_BASE_C_VIRTUAL               (PERIF_BASE_C_VIRTUAL + BB_OFFSET)
#define BB_BASE_U_VIRTUAL               (PERIF_BASE_U_VIRTUAL + BB_OFFSET)

#define KYPD_BASE_PHYSICAL              (PERIF_BASE_PHYSICAL + KYPD_OFFSET)
#define KYPD_BASE_C_VIRTUAL             (PERIF_BASE_C_VIRTUAL + KYPD_OFFSET)
#define KYPD_BASE_U_VIRTUAL             (PERIF_BASE_U_VIRTUAL + KYPD_OFFSET)

#define USIM_BASE_PHYSICAL              (PERIF_BASE_PHYSICAL + USIM_OFFSET)
#define USIM_BASE_C_VIRTUAL             (PERIF_BASE_C_VIRTUAL + USIM_OFFSET)
#define USIM_BASE_U_VIRTUAL             (PERIF_BASE_U_VIRTUAL + USIM_OFFSET)

#define SSP2_BASE_PHYSICAL              (PERIF_BASE_PHYSICAL + SSP2_OFFSET)
#define SSP2_BASE_C_VIRTUAL             (PERIF_BASE_C_VIRTUAL + SSP2_OFFSET)
#define SSP2_BASE_U_VIRTUAL             (PERIF_BASE_U_VIRTUAL + SSP2_OFFSET)

#define MEMSTK_BASE_PHYSICAL            (PERIF_BASE_PHYSICAL + MEMSTK_OFFSET)
#define MEMSTK_BASE_C_VIRTUAL           (PERIF_BASE_C_VIRTUAL + MEMSTK_OFFSET)
#define MEMSTK_BASE_U_VIRTUAL           (PERIF_BASE_U_VIRTUAL + MEMSTK_OFFSET)

#define SSP3_BASE_PHYSICAL              (PERIF_BASE_PHYSICAL + SSP3_OFFSET)
#define SSP3_BASE_C_VIRTUAL             (PERIF_BASE_C_VIRTUAL + SSP3_OFFSET)
#define SSP3_BASE_U_VIRTUAL             (PERIF_BASE_U_VIRTUAL + SSP3_OFFSET)



/////////////////////////////////////////////////////////////////////////////////////////
/* DEVICE STRUCTURES */
/////////////////////////////////////////////////////////////////////////////////////////

//
// MEMC
//
typedef struct
{
    volatile unsigned long    mdcnfg;
    volatile unsigned long    mdrefr;
    volatile unsigned long    msc0;
    volatile unsigned long    msc1;
    volatile unsigned long    msc2;
    volatile unsigned long    mecr;
    volatile unsigned long  rsvd0;
    volatile unsigned long    sxcnfg;
    volatile unsigned long    flycnfg;
    volatile unsigned long  rsvd1;
    volatile unsigned long    mcmem0;
    volatile unsigned long    mcmem1;
    volatile unsigned long    mcatt0;
    volatile unsigned long    mcatt1;
    volatile unsigned long    mcio0;
    volatile unsigned long    mcio1;
    volatile unsigned long    mdmrs;
    volatile unsigned long    boot_def;
    volatile unsigned long    arb_cntl;
    volatile unsigned long    bscntrp;
    volatile unsigned long    bscntrn;
    volatile unsigned long    lcdbscntr;
    volatile unsigned long    mdmrslp;
} MEMC_STRUCT, *PMEMC;


//
// DMAC
//
   // !this enum is unmodified from Cotulla!
enum XSC1_DmaSource {
  XSC1_UDC_Xmit = 0,
  XSC1_UDC_Rcv,
  XSC1_SDLC_Xmit,
  XSC1_SDLC_Rcv,
  XSC1_UART1_Xmit,
  XSC1_UART1_Rcv,
  XSC1_UART2_Xmit,
  XSC1_UART2_Rcv,
  XSC1_HSSP_Xmit,
  XSC1_HSSP_Rcv,
  XSC1_UART3_Xmit,
  XSC1_UART3_Rcv,
  XSC1_MCP_AudioXmit,
  XSC1_MCP_AudioRcv,
  XSC1_MCP_TelecomXmit,
  XSC1_MCP_TelecomRcv,
  XSC1_SSP_Xmit,
  XSC1_SSP_Rcv
};

typedef struct
{
    volatile unsigned long   ddadr;                  // descriptor address reg
    volatile unsigned long   dsadr;                  // source address register
    volatile unsigned long   dtadr;                  // target address register
    volatile unsigned long   dcmd;                   // command address register
}DMADescriptorChannelType;

typedef struct
{
	volatile unsigned long   dcsr[32];		        //DMA CSRs by channel
	volatile unsigned long rsvd0[0x8];
	volatile unsigned long   dalign;
	volatile unsigned long   dpcsr;
    volatile unsigned long rsvd1[0xE];
    volatile unsigned long    drqsr0;                //Dreq[0] Status
    volatile unsigned long    drqsr1;                //Dreq[1] Status
	volatile unsigned long    drqsr2;                //Dreq[1] Status
    volatile unsigned long rsvd2[0x1];
    volatile unsigned long    dint;                  //DMA interrupt Register
    volatile unsigned long rsvd3[0x3];
	volatile unsigned long    drcmr[64];             //On-chip device DMA request --> channel map registers [63:0]
	volatile DMADescriptorChannelType ddg[32];	    //32 channels of descriptor registers
    volatile unsigned long rsvd4[0x340];
	volatile unsigned long    drcmr2[11];             //On-chip device DMA request --> channel map registers [63:0]

} DMAC_REGS, *PDMAC;



//
// GENERIC UART structure
//
typedef struct
{
    volatile unsigned long    thr_rbr_dll;           //DLAB = 0  WO  8bit - Transmit Holding Register (THR)
                                                     //DLAB = 0  RO  8bit - Recieve Buffer Register (RBR)
                                                     //DLAB = 1  RW  8bit - Divisor Latch Low Register (DLL)
    volatile unsigned long    ier_dlh;               //DLAB = 0  RW  8bit - Interrupt Enable Register
    volatile unsigned long    iir_fcr;               //DLAB = X  RO  8bit - Interrupt Identification Register
    volatile unsigned long    lcr;                   //DLAB = X  RW  8bit - Line Control Register
    volatile unsigned long    mcr;                   //DLAB = X  RW  8bit - Modem Control Regiser
    volatile unsigned long    lsr;                   //DLAB = X  RO  8bit - Line Status Register
    volatile unsigned long    msr;                   //DLAB = X  RO  8bit - Modem Status Register
    volatile unsigned long    scr;                   //DLAB = X  RW  8bit - Scratchpad Register
    volatile unsigned long    irdasel;               //DLAB = X  RW  8bit - IrDA Select Register
    volatile unsigned long    fior;                  //DLAB = X  RO  FIFO Occupancy Register
    volatile unsigned long    abr;                   //DLAB = X  RW  Autobaud Control Register
    volatile unsigned long    acr;                   //DLAB = X Autobaud Count Register
} GEN_UART;

//
// FFUART
//
typedef GEN_UART *PFFUART;

//
// BTUART
//
typedef GEN_UART *PBTUART;

//
// STUART
//
typedef GEN_UART *PSTUART;

//
// I2C
//
typedef struct
{
    volatile unsigned long    ibmr;                  //I2C bus monitor register
    volatile unsigned long rsvd0;
    volatile unsigned long    idbr;                  //I2C data buffer register
    volatile unsigned long rsvd1;
    volatile unsigned long    icr;                   //I2C control register
    volatile unsigned long rsvd2;
    volatile unsigned long    isr;                   //I2C status register
    volatile unsigned long rsvd3;
    volatile unsigned long    isar;                  //I2C slave address register
    volatile unsigned long rsvd4;
    volatile unsigned long    i2ccr;                 //I2C clock count register
} I2C_REGS, *PI2C_REGS;

//
// I2S
//
typedef struct
{
    volatile unsigned long    sacr0;                 //Global control register
    volatile unsigned long    sacr1;                 //Serial Audio I2S/MSB justified control register
    volatile unsigned long rsvd0;
    volatile unsigned long    sasr0;                 //Serial audio I2S/MSB justified interface and fifo status register
    volatile unsigned long rsvd1;
    volatile unsigned long    saimr;                 //Serial audio intrerupt mask register
    volatile unsigned long    saicr;                 //Serial audio interrupt clear register
    volatile unsigned long rsvd2[17];
    volatile unsigned long    sadiv;                 //Audio clock divider register
    volatile unsigned long rsvd3[7];
    volatile unsigned long    sadr;                  //Serial audio data register
} I2S_REGS, *PI2S_REGS;

//
// AC97
//
typedef struct
{
    volatile unsigned long    pocr;                  //PCM out control register
    volatile unsigned long    picr;                  //PCM in control register
    volatile unsigned long    mccr;                  //Mic in control register
    volatile unsigned long    gcr;                   //Global Control Register
    volatile unsigned long    posr;                  //PCM out status register
    volatile unsigned long    pisr;                  //PCM in status register
    volatile unsigned long    mcsr;                  //Mic in status register
    volatile unsigned long    gsr;                   //global status register
    volatile unsigned long    car;                   //CODEC access register
    volatile unsigned long rsvd0[7];
    volatile unsigned long    pcdr;                  //audio fifo data register
    volatile unsigned long rsvd1[7];
    volatile unsigned long    mcdr;                  //mic in fifo data register
    volatile unsigned long rsvd2[39];
    volatile unsigned long    mocr;                  //Modem out control register
    volatile unsigned long rsvd3;
    volatile unsigned long    micr;                  //Modem in control register
    volatile unsigned long rsvd4;
    volatile unsigned long    mosr;                  //Modem out status register
    volatile unsigned long rsvd5;
    volatile unsigned long    misr;                  //modem in status register
    volatile unsigned long rsvd6[9];
    volatile unsigned long    modr;                  //Modem fifo data register
	volatile unsigned long rsvd7[47];
	volatile unsigned long  *v_pCodecBaseAddr[64];
} AC97_REGS, *PAC97_REGS;

//
// INTC, OST, and RTC register and bit definitions are
// defined in xllp_intc.h, xllp_ost.h and xllp_rtc.h
// and pulled in via intcbits.h and timerbits.h.
//


//
// POWER MANAGER and RESET CONTROL
//
typedef struct
{
    volatile unsigned long    pmcr;                  //Power manager control register
    volatile unsigned long    pssr;                  //Power manager sleep status register
    volatile unsigned long    pspr;                  //Power manager scratch pad register
    volatile unsigned long    pwer;                  //Power manager wake-up enable register
    volatile unsigned long    prer;                  //Power manager GPIO rising edge detect enable register
    volatile unsigned long    pfer;                  //Power manager GPIO falling edge detect enable register
    volatile unsigned long    pedr;                  //Power manager GPIO edge detect status register
    volatile unsigned long    pcfr;                  //Power manager general configuration register
    volatile unsigned long    pgsr0;                 //Power manager GPIO sleep state register for GPIO 31:0
    volatile unsigned long    pgsr1;                 //Power manager GPIO sleep state register for GPIO 63:32
    volatile unsigned long    pgsr2;                 //Power manager GPIO sleep state register for GPIO 95:64
    volatile unsigned long    pgsr3;                 //Power manager GPIO sleep state register for GPIO 120:96
    volatile unsigned long    rcsr;                  // **Reset controller status register**
    volatile unsigned long    pslr;                  //Power manager Sleep Mode Config
    volatile unsigned long    pstr;                  //Power manager Standby Mode Config
    volatile unsigned long    psnr;                  //Power manager Sense Mode Config
    volatile unsigned long    pvcr;                  //Power manager Voltage Change Control
    volatile unsigned long  rsvd0[15];
    volatile unsigned long    pcmd[32];              //Power manager I2C Command
    volatile unsigned long  rsvd1[32];
    volatile unsigned long    pibmr;                 //Power manager I2C Bus Monitor
    volatile unsigned long  rsvd2;
    volatile unsigned long    pidbr;                 //Power manager I2C Data Buffer
    volatile unsigned long  rsvd3;
    volatile unsigned long    picr;                  //Power manager I2C Control
    volatile unsigned long  rsvd4;
    volatile unsigned long    pisr;                  //Power manager I2C Status
    volatile unsigned long  rsvd5;
    volatile unsigned long    pisar;                 //Power manager I2C Slave Adx
} PMRC_REGS, *PPMRC_REGS;

//
// MMC
//
typedef struct
{
    volatile unsigned int    strpc;
    volatile unsigned int    stat;
    volatile unsigned int    clkrt;
    volatile unsigned int    spi;
    volatile unsigned int    cmdat;
    volatile unsigned int    resto;
    volatile unsigned int    rdto;
    volatile unsigned int    blkle;
    volatile unsigned int    nob;
    volatile unsigned int    prtbu;
    volatile unsigned int    imask;
    volatile unsigned int    ireg;
    volatile unsigned int    cmd;
    volatile unsigned int    argh;
    volatile unsigned int    argl;
    volatile unsigned int    res;
    volatile unsigned int    rxfifo;
    volatile unsigned int    txfifo;
} MMC_REGS, *PMMC_REGS;

//
// CLKMAN
//
typedef XLLP_CLKMGR_T   CLKMAN_REGS;


//
// SSP
//
typedef struct
{
    unsigned long    sscr0;							//SSP control register 0
    unsigned long    sscr1;							//SSP control register 1
    unsigned long    ssr;							//SSP status register
    unsigned long    ssitr;							//SSP interrupt test register
    unsigned long    ssdr;							//SSP data read/write register
} SSP_REGS, *PSSP_REGS;


//
// Bulverde UDC
//
typedef struct
{
    volatile unsigned long    udc_cr;
    volatile unsigned long    udc_icr0;
    volatile unsigned long    udc_icr1;
    volatile unsigned long    udc_isr0;
    volatile unsigned long    udc_isr1;
    volatile unsigned long    udc_fnr;
    volatile unsigned long    rsvd0[58];  //0x4060_0018 - 0x4060_00FF

    volatile unsigned long    udc_csr0;
    volatile unsigned long    udc_csrA;
    volatile unsigned long    udc_csrB;
    volatile unsigned long    udc_csrC;
    volatile unsigned long    udc_csrD;
    volatile unsigned long    udc_csrE;
    volatile unsigned long    udc_csrF;
    volatile unsigned long    udc_csrG;
    volatile unsigned long    udc_csrH;
    volatile unsigned long    udc_csrI;
    volatile unsigned long    udc_csrJ;
    volatile unsigned long    udc_csrK;
    volatile unsigned long    udc_csrL;
    volatile unsigned long    udc_csrM;
    volatile unsigned long    udc_csrN;

    volatile unsigned long    udc_csrP;
    volatile unsigned long    udc_csrQ;
    volatile unsigned long    udc_csrR;
    volatile unsigned long    udc_csrS;
    volatile unsigned long    udc_csrT;
    volatile unsigned long    udc_csrU;
    volatile unsigned long    udc_csrV;
    volatile unsigned long    udc_csrW;
    volatile unsigned long    udc_csrX;
    volatile unsigned long    rsvd1[40];  //0x4060_0160 - 0x4060_01FF

    volatile unsigned long    udc_bcr0;
    volatile unsigned long    udc_bcrA;
    volatile unsigned long    udc_bcrB;
    volatile unsigned long    udc_bcrC;
    volatile unsigned long    udc_bcrD;
    volatile unsigned long    udc_bcrE;
    volatile unsigned long    udc_bcrF;
    volatile unsigned long    udc_bcrG;
    volatile unsigned long    udc_bcrH;
    volatile unsigned long    udc_bcrI;
    volatile unsigned long    udc_bcrJ;
    volatile unsigned long    udc_bcrK;
    volatile unsigned long    udc_bcrL;
    volatile unsigned long    udc_bcrM;
    volatile unsigned long    udc_bcrN;

    volatile unsigned long    udc_bcrP;
    volatile unsigned long    udc_bcrQ;
    volatile unsigned long    udc_bcrR;
    volatile unsigned long    udc_bcrS;
    volatile unsigned long    udc_bcrT;
    volatile unsigned long    udc_bcrU;
    volatile unsigned long    udc_bcrV;
    volatile unsigned long    udc_bcrW;
    volatile unsigned long    udc_bcrX;
    volatile unsigned long    rsvd2[40];  //0x4060_0260 - 0x4060_02FF

    volatile unsigned long    udc_dr0;
    volatile unsigned long    udc_drA;
    volatile unsigned long    udc_drB;
    volatile unsigned long    udc_drC;
    volatile unsigned long    udc_drD;
    volatile unsigned long    udc_drE;
    volatile unsigned long    udc_drF;
    volatile unsigned long    udc_drG;
    volatile unsigned long    udc_drH;
    volatile unsigned long    udc_drI;
    volatile unsigned long    udc_drJ;
    volatile unsigned long    udc_drK;
    volatile unsigned long    udc_drL;
    volatile unsigned long    udc_drM;
    volatile unsigned long    udc_drN;

    volatile unsigned long    udc_drP;
    volatile unsigned long    udc_drQ;
    volatile unsigned long    udc_drR;
    volatile unsigned long    udc_drS;
    volatile unsigned long    udc_drT;
    volatile unsigned long    udc_drU;
    volatile unsigned long    udc_drV;
    volatile unsigned long    udc_drW;
    volatile unsigned long    udc_drX;
    volatile unsigned long    rsvd3[40];  //0x4060_0360 - 0x4060_03FF

    volatile unsigned long    udc_cr0;
    volatile unsigned long    udc_crA;
    volatile unsigned long    udc_crB;
    volatile unsigned long    udc_crC;
    volatile unsigned long    udc_crD;
    volatile unsigned long    udc_crE;
    volatile unsigned long    udc_crF;
    volatile unsigned long    udc_crG;
    volatile unsigned long    udc_crH;
    volatile unsigned long    udc_crI;
    volatile unsigned long    udc_crJ;
    volatile unsigned long    udc_crK;
    volatile unsigned long    udc_crL;
    volatile unsigned long    udc_crM;
    volatile unsigned long    udc_crN;

    volatile unsigned long    udc_crP;
    volatile unsigned long    udc_crQ;
    volatile unsigned long    udc_crR;
    volatile unsigned long    udc_crS;
    volatile unsigned long    udc_crT;
    volatile unsigned long    udc_crU;
    volatile unsigned long    udc_crV;
    volatile unsigned long    udc_crW;
    volatile unsigned long    udc_crX;
    volatile unsigned long    rsvd4[40];  //0x4060_0460 - 0x4060_04FF

    //Note:  0x4060_0500 - 0x406F_FFFF is reserved.

} UDC_REGS, *PUDC_REGS;



#endif

